Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device capable of restraining a leakage current at a n-p junction of source/drain regions and a manufacturing method of the semiconductor device. A trench is formed in the source/drain regions, a main surface of the source/drain regions is removed at a time of forming the trench and a surface area of the source/drain regions is increased as compared with that before forming the trench. In this manner, a stress per unit area concentrated on the source/drain regions in the vicinity of ends of an isolating oxide film is reduced, and any occurrence of minute defects is restrained. As a result, leakage current caused by any minute defects due to the stress is reduced, and a refresh pause time is prolonged, and in other words, characteristics of a refresh operation can be improved.

BACKGROUND OF THE INVENTION

1. 1. Field of the Invention

2. The present invention relates to a semiconductor device and amanufacturing method thereof and, more particularly, to a semiconductordevice which restrains a leakage current in a n-p junction or acapacitor insulating film of a memory cell of a DRAM (Dynamic RandomAccess Memory), and to a manufacturing method thereof.

3. 2. Description of the Background Art

4. Semiconductor memories are generally classified into three types: aDRAM (Dynamic Random Access Memory), a flash memory, and a SRAM (StaticRandom Access Memory). In the DRAM, data are refreshed and storedtherein constantly, but when power is shut off thereto, the data oncestored are lost. In the flash memory, data are perpetually storedtherein and never lost even if power is shut off thereto. Therefore, theflash memory is referred to as a non-volatile memory. In the SRAM, dataare not required to be refreshed, and when power thereto is shut off,the data once stored are lost. In this manner, each type of thesesemiconductor memories has its own characteristics, and is selected foruse in conformity with their characteristics.

5. The DRAM is a leading memory occupying a greater production quantityof semiconductor memories at present. A DRAM includes a memory cellarray serving as a storage region for storing a large quantity ofstorage information, and a peripheral circuit section for performing apredetermined input/output operation with respect to the memory cellarray. The memory cell array further includes a plurality of memorycells arranged to perform as a minimum storage unit. Each memory cellbasically includes a capacitor, and a MOS (Metal Oxide Semiconductor)transistor. In operation, whether or not a certain charge is stored inthe capacitor is judged, and the judgment is associated with data of “0”and “1”, whereby the storage information is processed.

6.FIG. 34 shows an equivalent circuit of a memory cell of a backgroundDRAM and in which reference numeral 201 designates a capacitor, andnumeral 202 designates a cell transistor. The capacitor 201 and the celltransistor 202 form a memory cell 200. Numeral 203 is a bit line,numeral 204 is a word line, and numeral 205 is a sense amplifier. Asshown in FIG. 34, the capacitor 201 is connected to one of source/drainregions of the cell transistor 202, and the bit line 203 is connected tothe other of source/drain regions of the cell transistor 202. Further, agate electrode of the cell transistor 202 is connected to the word line204, and the bit line 203 is connected to the sense amplifier 205.

7. The term “source/drain” is used herein because this element serves asa “source” to supply a carrier or as a “drain” to remove a carrier,depending on read or write of information.

8.FIG. 35 is a sectional view showing a construction of a backgroundmemory cell of which partially hidden parts are indicated by brokenlines. In FIG. 35, reference numeral 101 is a semiconductor substrate,numeral 102 is an isolating oxide film forming a STI (Shallow TrenchIsolation) in which one element is electrically insulated from otherelements. Numeral 103 is a gate oxide film, and numeral 104 is a gateelectrode forming the word line 204. Numerals 105 and 106 aresource/drain regions formed on left and right sides under the gateelectrode 104. Numeral 107 is a side wall which is an insulating filmcoating the gate electrode 104. Numeral 1010 are polysilicon plugs, oneof which is connected to the drain region 106, and another of which isconnected to a storage node contact 1017 later described. Numeral 1011are polysilicon plugs, one of which is connected to the source region,and another of which is connected to the bit line 203 indicated bybroken lines in FIG. 35. Numerals 1012 and 1013 are silicon oxide filmsand numeral 1014 is a silicon nitride film. These elements 1012-1014form an interlayer insulating film. Numeral 1015 is a trench which isprovided in such a manner to be open in the interlayer insulating film.Numeral 1017 is a storage node contact formed in the trench 1015.Numeral 1019 is a storage node, numeral 1020 is a capacitor insulatingfilm, and numeral 1021 is a cell plate. The capacitor insulating film1020 is made of a nitride titanium film (TiN) and a tantalum oxide film(Ta₂O₅) formed on the surface thereof. The cell plate 1021 is composedof a polysilicon which includes n-type impurities. A capacitor 1022 isformed by the storage node 1019, the capacitor insulating film 1020 andthe cell plate 1021.

9. A charge stored in the capacitor 201 as a storage information isgradually discharged due to a leakage current in the n-p junctionbetween the source/drain regions 105, 106 and the semiconductorsubstrate 101 or in the capacitor insulating film 1020, etc. Anoperation of timely injecting a charge is required in order to maintainstorage in the DRAM. This operation is called a “refresh”, in whichinformation written in the capacitor 201 is judged by the senseamplifier 205. That is, the read or write of information is performed sothat a new charge is supplied when it is judged that a charge isinjected in the capacitor 201, and that the charge is exhausted in thecapacitor 201 when it is judged that no charge is injected.

10. In addition, the refresh is performed by applying a voltage to theselected gate electrode 104 and the source/drain region 105 and byperforming the read or write of the information stored in the capacitor201, as mentioned above.

11. In the background semiconductor device, however, information is lostdue to generation of leakage current from the n-p junction of thestorage node, the storage node contact and the source/drain region, inaddition to the loss of information due to this read operation. In viewof preventing the loss of information due to the leakage current, therehas been a problem that the refresh must be performed on the informationstored in every memory cell within a relatively short period of about 1msec to several hundred msec. This refresh results in an increase inpower consumption.

12. There has been another problem that, as the information stored inthe memory cells cannot be read during the refresh, a refresh interval(refresh pause time) is shortened. If the refresh pause time is short,efficiency of data use per operating time is lowered.

13. There has been a further problem that minute defects are producedaround the end of the isolating oxide film due to a stress caused by adifference in the coefficient of cubic expansion between thesemiconductor substrate and the isolating oxide film, and a leakagecurrent is generated due to such minute defects, which also shortens therefresh pause time.

SUMMARY OF THE INVENTION

14. The present invention has been made to solve the above-discussedproblems and has as one object to provide a novel semiconductor devicecapable of restraining a leakage current of a n-p junction of asource/drain region and a manufacturing method thereof.

15. Another object of the present invention is to provide a novelsemiconductor device capable of restraining a leakage current caused byminute defects produced due to stress around an end of an isolatingoxide film and a manufacturing method thereof.

16. A further object of the present invention is to provide a novelsemiconductor device capable of restraining a leakage current of acapacitor insulating film flowing through a storage node contact and amanufacturing method thereof.

17. A novel semiconductor device according to the present inventionincludes a semiconductor substrate. An isolating oxide film is formed onan isolated region of a main surface of the semiconductor substrate. Apair of source/drain regions is formed in an active region surrounded bythe isolated region of the main surface of the semiconductor substrate.A trench is formed in the source/drain regions. A gate electrode isformed on the main surface of the active region of the semiconductorsubstrate through an insulating film. An interlayer insulating film isformed to coat the isolating oxide film, the source/drain regions, thetrench, and the gate electrode. A wiring layer reaches the trenchthrough an opening provided on the interlayer insulating film, and acapacitor is connected to either of the source/drain regions through thewiring layer.

18. In the mentioned novel semiconductor device, since the trench isformed in the source/drain regions, the main surface of the source/drainregions is removed at the time of forming the trench, and a surface areaof the source/drain regions is increased as compared with that beforeforming the trench. Accordingly, a stress per unit area concentrated onthe source/drain regions in the vicinity of ends of the isolating oxidefilm is reduced, and an occurrence of minute defects is restrained. As aresult, any leakage current caused by minute defects due to stress isreduced, and the refresh pause time is prolonged, in other words,characteristics of refresh can be improved.

19. A novel semiconductor device in another aspect of the presentinvention also includes a semiconductor substrate. An isolating oxidefilm is formed on an isolated region of a main surface of thesemiconductor substrate. A pair of source/drain regions is formed in anactive region surrounded by the isolated region of the main surface ofthe semiconductor substrate. A gate electrode is formed on the mainsurface of the active region of the semiconductor substrate through aninsulating film. An interlayer insulating film is formed to coat theisolating oxide film, the source/drain regions, the trench, and the gateelectrode. A wiring layer is formed by filling up a contact holereaching the source/drain regions through an opening provided on theinterlayer insulating film. A capacitor is connected to either of thesource/drain regions through the wiring layer, and a film forrestraining a leakage current is formed in the wiring layer apart fromthe capacitor.

20. In the mentioned novel semiconductor device, since the film forrestraining a leakage current is formed at a portion isolated from thecapacitor in the wiring layer connecting the capacitor and thesource/drain regions, the leakage current is restrained from flowingbetween the capacitor and the source/drain regions when no voltage isapplied, and thus the refresh pause time can be prolonged.

21. A novel manufacturing method of a semiconductor device according tothe present invention includes a step of forming an isolating oxide filmon an isolated region of a main surface of a semiconductor substrate. Agate electrode is formed on the main surface of the semiconductorsubstrate through an insulating film. A pair of source/drain regions isformed in an active region surrounded by the isolated region of theprincipal surface of the semiconductor substrate. A side wall is formedon a side of the gate electrode. A trench is formed by etching theprincipal surface of the source/drain regions. A first wiring layer isformed by filling up the trench with a first conductive material. Aninterlayer insulating film is formed to coat the isolating oxide film,the source/drain regions, the trench, and the gate electrode. An openingis formed to reach from a surface of the interlayer insulating film to asurface of the first wiring layer. A second wiring layer is formed byfilling up the opening with a second conductive material, and acapacitor is formed to be connected to either of the source/drainregions through the first and second wiring layers.

22. In the mentioned novel manufacturing method of the semiconductordevice, since the trench is formed on the surface of the source/drainregions, stress concentrated on the source/drain region in the vicinityof the end of the isolating oxide film and on the semiconductorsubstrate is reduced, and any occurrence of minute defects isrestrained. As a result, any leakage current caused by minute defectsdue to the stress is reduced, and the refresh pause time is prolonged,in other words, characteristics of refresh can be improved.

23. A novel manufacturing method of a semiconductor device in anotheraspect of the present invention also include a step of forming anisolating oxide film on an isolated region of a main surface of asemiconductor substrate. A gate electrode is formed on the main surfaceof the semiconductor substrate through an insulating film. A pair ofsource/drain regions is formed in an active region surrounded by theisolated region of the main surface of the semiconductor substrate. Aside wall is formed on a side of the gate electrode. An interlayerinsulating film is formed to coat the isolating oxide film, thesource/drain regions, the trench, and the gate electrode. An opening isformed for forming a wiring layer connected electrically to either ofthe source/drain regions on the interlayer insulating film. A firstwiring layer of the wiring layer is formed by filling up to a halfway ofthe opening with a first material, a second wiring layer of the wiringlayer is formed on the first wiring layer formed on the opening byfilling up to a halfway of the opening with a second material, and athird wiring layer of the wiring layer is formed on the second wiringlayer formed on the opening by filling up with the first material. Acapacitor is formed to be connected electrically to the wiring layerincluding the first, second, and third wiring layers.

24. In the mentioned novel manufacturing method of the semiconductordevice, since the film for restraining the leakage current is formed ata portion isolated from the capacitor in the wiring layer connecting thecapacitor and the source/drain regions, leakage current is restrainedfrom flowing between the capacitor and the source/drain regions when novoltage is applied, and thus the refresh pause time can be prolonged.

BRIEF DESCRIPTION OF THE DRAWING

25. A more complete appreciation of the present invention and many ofthe attendant advantages thereof will be readily obtained as the samebecomes better understood by reference to the following detaileddescription when considered in connection with the accompanyingdrawings, wherein:

26.FIG. 1 is a sectional view showing a construction of a semiconductordevice according to a first preferred embodiment of the presentinvention, and in which partially hidden parts are indicated by brokenlines;

27. FIGS. 2 to 9 are sectional views showing sequential steps of amanufacturing method of the semiconductor device shown in FIG. 1according to the present invention;

28. FIGS. 10 to 15 are sectional views showing a semiconductor deviceaccording to a second preferred embodiment of the present invention;

29.FIG. 16 is a sectional view showing a step of a manufacturing methodof the semiconductor device shown in FIG. 10;

30.FIG. 17 is a sectional view showing a step of a manufacturing methodof the semiconductor device shown in FIG. 12;

31.FIG. 18 is a sectional view showing a step of a manufacturing methodof the semiconductor device shown in FIG. 14;

32.FIG. 19 is a sectional view showing a semiconductor device accordingto a third preferred embodiment of the present invention;

33.FIGS. 20, 22 and 23 are sectional views showing sequential steps of amanufacturing method of the semiconductor device shown in FIG. 19according to the present invention;

34.FIGS. 21 and 24 are plan views showing a step of a manufacturingmethod of the semiconductor device shown in FIG. 19;

35. FIGS. 25 to 28 are sectional views showing a semiconductor deviceaccording to a fourth preferred embodiment of the present invention;

36.FIG. 29 is a graph to explain a relation between depth and impurityconcentration of the semiconductor substrate according to the first andfourth preferred embodiments of the present invention;

37.FIG. 30 is a sectional view showing a step of a manufacturing methodof the semiconductor device shown in FIG. 25;

38.FIGS. 31 and 33 are sectional views showing a step of a manufacturingmethod of the semiconductor device shown in FIG. 26;

39.FIG. 32 is a plan view showing a step of a manufacturing method ofthe semiconductor device shown in FIG. 26;

40.FIG. 34 is a diagram showing an equivalent circuit of a memory cellof a semiconductor device according to background art; and

41.FIG. 35 is a sectional view showing a construction of a memory cellaccording to the background art, and in which partially hidden parts areindicated by broken lines.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

42. A semiconductor device according to a first preferred embodiment ofthe present invention and a manufacturing method thereof are hereinafterdescribed.

43.FIG. 1 is a sectional view showing a construction of a semiconductordevice according to a first preferred embodiment of the presentinvention, and in which partially hidden parts are indicated by brokenlines. An equivalent circuit of a memory cell of a DRAM which is asemiconductor device according to the present invention is the same asthe circuit shown in FIG. 34. Referring to FIG. 1, reference numeral 1designates a p-type semiconductor substrate, numeral 2 designates anisolating oxide film for electrically insulating one element fromanother and which is formed on an isolated region of a main surface ofthe semiconductor substrate 1. Numeral 3 is a gate oxide film, numeral 4is a gate electrode forming a word line of the memory cell, and numerals5 and 6 are source/drain regions formed on left and right sides underthe gate electrode 4. Numeral 7 is a side wall serving as an insulatingfilm to cover the gate electrode 4, and numeral 8 is a trench formed inthe source/drain regions 5, 6 to be deeper than the source/drain regions5, 6.

44. Numeral 10 is a silicon carbide plug (SiC) in which the source anddrain are arranged not to short each other. Numeral 11 is a siliconcarbide plug (SiC) having one end connected to the source region 5 andanother end connected to the bit line 203 of the memory cell indicatedby the broken line in the FIG. 1 Numerals 12 and 13 are nitride andoxide films (SiON films), and numeral 14 is a silicon nitride film, eachfilm forming an interlayer insulating film. Numeral 15 is a trenchopened in the interlayer insulating film. Numeral 17 is a storage nodecontact formed in the trench and forming a second wiring layer. Numeral19 is a storage node, numeral 20 is a capacitor insulating film composedof a titanium nitride film and a tantalum oxide film, and numeral 21 isa cell plate. A capacitor 22 is formed by the storage node 19, thecapacitor insulating film 20, and the cell plate 21.

45. This semiconductor device is a n-type MOS transistor, in which thep-type semiconductor substrate 1 includes boron of about 1×10¹⁵/cm³, forexample, and the gate electrode 4 has a gate length L=0.1 to 0.2 μm andincludes n-type impurities such as phosphorus or arsenic. Thesource/drain regions 5 and 6 are also formed by injecting n-typeimpurity ion such as phosphorus or arsenic, and their concentration ofimpurities is about 1× 10¹⁷ to 1×10¹⁸/cm³. The silicon carbide plugs 10and 11 are 6H—SiC or 4H—SiC, and include nitrogen of about 1×10¹⁸/cm³ to1×10²⁰/cm³ as n-type impurities. Further, an energy band gap of 6H—SiCis 2.86 eV, and that of 4H—SiC is 3.25 eV. An energy band gap of siliconis 1.12 eV. Although silicon carbide (SiC) is taken as an exampleherein, any other material is preferable which has an energy hand gaplarger than silicon.

46. A depth of the trench 8 is about 0.01 μm to 0.1 μm, and the trench 8is preferably formed in such a manner to go through the source/drainregion 5.

47. The capacitor insulating film 20 is composed of a titanium nitridefilm of about 100 Å to 500 Å and a tantalum oxide film of about 50 Å to100 Å formed on the surface thereof. Capacity is increased by thetantalum oxide film of high dielectric constant, and tantalum atom (Ta)is prevented by the titanium nitride film from being diffused from thestorage node 19 to other parts. The cell plate 21 is formed ofpolysilicon which includes phosphorus of about 1×10²⁰/cm³. Storage node19 is formed of polysilicon which includes n-type impurities of1×10²⁰/cm³ to 1×10²¹/cm³ such as phosphorus or arsenic. It may also bepreferable to employ a fluoride and oxide film (SiOF) instead of thenitride and oxide films 12 and 13. As the dielectric constant of thefluoride and oxide film is small as compared with the silicon oxidefilm, interlayer parasitic capacity is reduced, whereby it is possibleto improve the operating speed of the transistor.

48. In each active region surrounded by the isolating oxide film 2, twocell transistors are formed, and a gate electrode of a transistor usedin the memory cell of another address is formed on the isolating oxidefilm 2.

49. Although a STI (Shallow Trench Isolation) is illustrated herein asthe isolating oxide film, any other isolation oxide film can be employedsuch as LOCOS (Local Oxidation of Silicon). In addition, a channel layeror a channel cut layer can be formed in the semiconductor substrate 1,when required.

50. In the refresh operation, by applying a voltage simultaneously toone word line selected among the word lines connected to the gateelectrode 4 and to a bit line selected among the bit lines connected tothe source/drain region 5 through the silicon carbide plug 1, one of thetransistors in the memory cell is turned on. By amplifying a smallcurrent flowing at this moment using the sense amplifier, an informationwritten in the capacitor 22 is read out. Likewise at the time of writingan information, by applying a voltage to the gate electrode 4 and to thesource/drain region 5, the transistor is turned on and a current flows,whereby information is written in the capacitor 22 through the drain 6,the silicon carbide plug 10, and the storage node contact 17. Theinformation to be written in the capacitor 22 is decided by the voltageapplied to the source/drain region 5 (bit line). For example, a sourcevoltage V_(CC)=2V, a substrate bias voltage V_(BB)=−1V, a drain voltageV_(DD)=2V, and a gate voltage is increased to about V_(G)=4V andapplied.

51. In the semiconductor device according to the first preferredembodiment of the present invention, since the silicon carbide plug 10connecting the source/drain region 6 to the storage node contact 17 isformed by 4H—SiC or 6H—SiC having an energy band gap larger thansilicon, it is possible to restrain both current generated in theprocess of Shockley-Read-Hall (SRH) and tunnel current between bands,whereby the junction leakage current in the vicinity of the source/drainregions can be reduced. As a result, the refresh pause time isprolonged, that is, characteristics of refresh are improved andreliability of the semiconductor device is also improved.

52. Further, since the trench 8 is formed, the main surface of thesource/drain region 6 is removed at the time of forming the trench 8,and the surface area of the source/drain region 6 is increased ascompared with that before forming the trench 8. Accordingly, a stressper unit area concentrated on the source/drain region 6 in the vicinityof ends of the isolating oxide film 2 or on the p-type semiconductorsubstrate 1 is reduced, and thereby any occurrence of minute defects isrestrained. As a result, any leakage current caused by minute defectsdue to stress is reduced, and the refresh pause time is prolonged, inother words, characteristics of refresh can be improved. Furthermore,since the silicon carbide plug 10 is so arranged as to go through thesource/drain region 6, pollution on the surface of the source/drainregion 6 is removed, whereby any defective junction is restrained. Inaddition, as the energy band gap of the silicon carbide plug 10 islarge, the leakage current can be restrained all the more, and therefresh pause time can be prolonged.

53. If the fluoride and oxide film is employed, for example, as aninterlayer insulating film and the dielectric constant of this fluorideand oxide film is low as compared with the silicon oxide film,interlayer parasitic capacity is reduced, whereby operating speed of thetransistor can be improved.

54. FIGS. 2 to 9 are sectional views showing sequential steps of amanufacturing method of the semiconductor device shown in FIG. 1according to a first preferred embodiment of the present invention.Referring to FIGS. 2 to 9, reference numeral 9 is a silicon carbidelayer (SiC), numeral 16 is a n-type polysilicon, and numeral 18 is asilicon oxide film.

55. First, as shown in FIG. 2, after forming a shallow trench in theisolated region of the semiconductor substrate 1 and filling up thetrench with an oxide film, the surface is flattened by CMP (ChemicalMechanical Polishing) and the isolating oxide film 2 is formed. A STI(Shallow Trench Isolation) is herein illustrated as the isolating oxidefilm 2. Although the surface of the STI is coincident to the height ofthe surface of the semiconductor substrate 1 in FIG. 2, the surface isnot always coincident thereto. Any other shape of an isolating oxidefilm such as LOCOS (Local Oxidation of Silicon) is also satisfiable.

56. Then, after performing channel injection or channel cut injectionwith impurities such as boron or boron fluoride when required (notillustrated), the gate oxide film 3 is formed by thermal oxidation asshown in FIG. 3. Then, the gate electrode 4 composed of a polysiliconfilm including n-type impurities such as phosphorus or arsenic isformed.

57. Then, after forming the source/drain regions 5 and 6 by ionimplantation of n-type impurities such as phosphorus or arsenic, asilicon oxide film is formed on the entire surface, which is then etchedback to form the side wall 7. At this time, the side wall 7 may beformed either of silicon nitride film or TEOS (TetraethylOrthosilicate).

58. As shown in FIG. 4, by etching the source/drain regions 5, 6 and thesemiconductor substrate 1 using the isolating oxide film 2 and the sidewall 7 as masks, a trench 8 having a depth of 0.01 μm to 0.1 μm from thesurface of the semiconductor substrate 1 and piercing through thesource/drain regions 5 and 6 in a self-aligned manner is formed. Then,the silicon carbide layer (SiC) 9 of which surface includes nitrogenserving as n-type impurities is subject to an epitaxial growth.

59. Then, masking a part except the gate electrode 4, an etching isperformed as shown in FIG. 5, whereby the silicon carbide plugs 10 and11 including nitrogen in the amount of about 1×10¹⁸ to 1×10²⁰/cm³ areformed.

60. Then, after depositing a nitride and oxide film (SiON) 12 on theentire surface, a mask patterning is performed, whereby a trenchreaching the silicon carbide plug 11 is formed (not illustrated).Thereafter, by depositing a tungsten layer, flattening the surface withCMP, mask patterning and etching, the bit line is formed (notillustrated).

61. Further, as shown in FIG. 6, after depositing the nitride and oxidefilm 13 and the silicon oxide film 14 on the entire surface, a maskpatterning and an etching are performed, whereby the trench 15 of whichdepth from the surface of the nitride film 14 is about 0.1 μm to 0.3 μmis formed.

62. Then, as shown in FIG. 7, after forming the n-type polysilicon film16 including n-type impurities such as phosphorus or arsenic in anamount of about 1×10²⁰ to 1×10²¹/cm³ on the entire surface and fillingup the trench 15, a flattening is performed by CMP until reaching thesame height as the surface of the silicon nitride film 14, and thestorage node contact 17 is formed.

63. Then, as shown in FIG. 8, after forming the silicon oxide film 18 onthe entire surface except the upper region of the storage node contact17 where the storage node 19 is formed, a n-type polysilicon filmincluding phosphorus or arsenic which is the same impurity as thestorage node contact 17 is deposited. Although a cylindrical storagenode is illustrated in the drawing, any other shape such as a fin typestorage node may be formed, and subsequently a treatment such asroughening of the surface is performed, when required.

64. After removing the silicon oxide film 18, as shown in FIG. 9, atantalum nitride film (TiN) is formed on the entire surface and atantalum oxide film (Ta₂O₅) of about 50 Å to 100 Å is further formedthereon, whereby the capacitor insulating film 20 is formed. Thereafter,a polysilicon including phosphorus of about 1×10²⁰/cm³ is deposited onthe entire surface of the polysilicon, and a patterning is performed,whereby the cell plate 21 is formed. The capacitor insulating film 20and the cell plate 21 may be either formed in such a manner as to coatthe entire surface of the memory cell region or may be formed in such amanner as to be divided into plural parts. In this manner, thesemiconductor device shown in FIG. 1 is formed.

65. In a case of forming the memory cell and the peripheral circuit inone substrate, the mentioned arrangement is performed at the time offorming the capacitor, after masking to expose only the memory cellregion.

66. In the manufacturing method of the semiconductor device according tothe first preferred embodiment of the present invention, since thetrench 8 is formed in a self-aligned manner using the side wall 7 andthe isolating oxide film 2 as masks and the silicon carbide plug 10 isformed, pollution on the surface of the source/drain regions 6 isremoved by a simple process, and any stress concentrated on thesource/drain region 6 in the vicinity of the end of the isolating oxidefilm and on the p-type semiconductor substrate 1 is reduced, and anyoccurrence of minute defects are restrained. As a result, any leakagecurrent caused by minute defects due to stress is reduced, and therefresh pause time is prolonged, in other words, characteristics ofrefresh can be improved.

67. Further, since the plug 10 connecting the source/drain region 6 tothe storage node contact 17 is formed by 4H—SiC or 6H—SiC having anenergy band gap larger than silicon, it is possible to restrain bothcurrent generated in the process of Shockley-Read-Hall (SRH) and tunnelcurrent between bands, and the area of n-p junction formed by thesource/drain region 6 and the p-type semiconductor substrate 1 isreduced, whereby a defective junction is restrained, and junctionleakage current in the vicinity of the source/drain region 6 can bereduced.

68. A semiconductor device according to a second preferred embodiment ofthe present invention and a manufacturing method thereof are hereinafterdescribed.

69. FIGS. 10 to 15 are sectional views showing the semiconductor deviceaccording to the second preferred embodiment of the present invention.

70. Referring to FIGS. 10 to 15, reference numerals 23 and 24 arepolysilicon plugs, and numeral 25 is a polysilicon film. In FIGS. 10 to15, like reference numerals are designated to the same parts as orequivalents in the foregoing first preferred embodiment.

71. First, referring to FIG. 10, a thickness of the polysilicon film 25is about 1 nm, and in a case of including n-type impurities such asphosphorus or arsenic, a concentration of the impurities is about 1×10¹⁶to 1×10¹⁸/cm³, but it is not always necessary to include the impurities.What is different about this second preferred embodiment from theforegoing first preferred embodiment is that the trench 8 is not formed.

72. However, the polysilicon film 25 is so thin that a tunnel currentflows by applying a normal write or read voltage.

73. As shown in FIG. 11, the polysilicon film 25 may be formed on theboundary surface between the storage node contact 17 and the polysiliconplug 23. It is also possible for the polysilicon film 25 to be formed inan internal part of the polysilicon plug 23 as shown in FIG. 12, or on aboundary surface between the polysilicon plug 23 and the source/drainregion 6 as shown in FIG. 13. However, as a contact resistance dependenton a surface condition of the source/drain region 6 is generated in thejunction part between the polysilicon plug 23 and the source/drainregion 6, the resistance is further increased and a data write speed islowered if forming the polysilicon film 25 on this part. Therefore, itis preferred that the polysilicon film 25 is formed in such a manner asto be separate from the junction surface between the polysilicon plug 23and the source/drain region 6.

74. In the semiconductor device according to the second preferredembodiment of the present invention, since the polysilicon film 25 isformed having a small impurity concentration, as compared with thestorage contact 17 which is formed of polysilicon including phosphorusor arsenic of about 1×10²⁰ to 1×10²¹/cm³ as n-type impurities, and withthe polysilicon plug 23 which includes n-type impurities such asphosphorus or arsenic of about 1×10¹⁸ to 1×10²⁰/cm³, resistance of thepolysilicon film 25 is increased. As a current hardly flows withoutapplication of a voltage in the polysilicon film 25, leakage current isrestrained from flowing between the storage node 19 and the source/drainregion 6, and a refresh pause time can be prolonged.

75. Further, when forming a silicon carbide film which includes n-typeimpurities such as nitrogen of about 1×10¹⁸ to 1×10²⁰/cm³instead of thepolysilicon film 25, as the energy band gap is increased, leakagecurrent can be reduced, and the refresh pause time can be prolonged.

76. When the polysilicon plug 23 is not formed, the polysilicon film 25can be preferably formed on the internal part of the storage nodecontact 17 as shown in FIG. 14 or on the boundary surface between thestorage node contact 17 and the source/drain region 6 as shown in FIG.15. However, a contact resistance dependent on the surface condition ofthe source/drain region 6 is generated at the junction part between thestorage node contact 17 and the source/drain region 6. Accordingly, ifforming the polysilicon film 25 on such a part, the resistance isfurther increased and the data write speed is lowered. Therefore, it ispreferred that the polysilicon film 25 is formed in such a manner to beseparate from the junction part between the storage node contact 17 andthe source/drain region 6 as shown in FIG. 14.

77. FIGS. 16 to 18 are sectional views each showing a step of amanufacturing method of the semiconductor device according to the secondpreferred embodiment of the present invention. In FIGS. 16 to 18,reference numeral 26 is a polysilicon film, and numeral 27 is a siliconfilm.

78. First, a manufacturing method of the semiconductor device shown inFIG. 10 is hereinafter described.

79. After forming the isolating oxide film 2, the gate oxide film 3, thegate electrode 4, the source/drain regions 5 and 6, and the side wall 7on the semiconductor substrate 1 in the same manner as in the foregoingfirst preferred embodiment, the polysilicon plugs 23 and 24 are formedin the same manner as formation of the silicon plugs 10, 11 in the firstpreferred embodiment, and the nitride and oxide films 12 and 13, thesilicon nitride film 14, and the trench 15 are formed.

80. Then, the n-type polysilicon film 16 including n-type impuritiessuch as phosphorus or arsenic of about 1×10²⁰ to 1×10²¹/cm³ is formed onthe entire surface and etched back, whereby the trench 15 is filled upto a halfway thereof. Thereafter, as shown in FIG. 16, a polysiliconfilm 26 which includes n-type impurities such as phosphorus or arsenicof about 1 ×10¹⁶ to 1×10¹⁸/cm³ or does not include any n-type impurityis formed on the entire surface and etched back, whereby the polysiliconfilm 25 of about 1 nm in thickness is formed.

81. Then, after forming a polysilicon film 17 on the entire surface soas to fill up the trench 15 completely, the surface is flattened by CMPin the same manner as in the first preferred embodiment until reachingthe same height as the surface of the silicon nitride film 14, and thecapacitor 22 is formed further thereon.

82. After forming the trench 15, when the polysilicon film 26 is formedbefore forming the n-type polysilicon film 16, a semiconductor, in whichthe polysilicon film 25 is formed on the boundary surface between thestorage node contact 17 and the polysilicon plug 23 as shown in FIG. 11,is obtained.

83. A manufacturing method of the semiconductor device shown in FIG. 12is hereinafter described.

84. In the same manner as in the first preferred embodiment, theisolating oxide film 2, the gate oxide film 3, the gate electrode 4, thesource/drain regions 5 and 6, and the side wall 7 are formed on thesemiconductor substrate 1.

85. Then, the polysilicon film including n-type impurities such asphosphorus or arsenic of about 1×10¹⁸ to 1×10²⁰/cm³ is formed on theentire surface and etched back, whereby a part of the polysilicon plugs23 and 24 is formed on the surface of the source/drain regions 5 and 6.Thereafter, as shown in FIG. 17, a masking is performed with the siliconnitride film 27 so as to expose only the surface of the source/drainregion 6. Then, the polysilicon film 26 which includes n-type impuritiessuch as phosphorus or arsenic of about 1×10¹⁶ to 1× 10¹⁸/cm³ or does notinclude any n-type impurity is formed on the entire surface and etchedback, whereby the polysilicon film 25 of about 1 nm in thickness isformed as shown in FIG. 12. The silicon nitride film 27 is then removed.

86. In the same manner as in the formation of the silicon carbide plugs10, 11 in the first preferred embodiment, the polysilicon plugs 23 and24 are formed, and the nitride and oxide films 12, 13, the siliconnitride film 14, the trench 15, the storage node contact 17, and thecapacitor 22 are also formed.

87. After forming the side wall 7, when the polysilicon film 26 isformed before forming the polysilicon plugs 23 and 24, a semiconductor,in which the polysilicon film 25 is formed on the boundary surfacebetween the source/drain region 6 and the polysilicon plug 23 as shownin FIG. 13, is obtained.

88. A manufacturing method of the semiconductor device shown in FIG. 14is hereinafter described.

89. After forming the isolating oxide film 2, the gate oxide film 3, thegate electrode 4, the source/drain regions 5 and 6, the side wall 7, thenitride and oxide films 12 and 13, and the silicon nitride film 14 onthe semiconductor substrate 1, in the same manner as in the firstpreferred embodiment, the trench 15 reaching the source/drain region 6is formed.

90. Then, as shown in FIG. 18, the n-type polysilicon film 16 includingn-type impurities such as phosphorus or arsenic of about 1×10²⁰ to1×10²¹/cm³ is formed on the entire surface and etched back, whereby thetrench 15 is filled up to a halfway thereof. Thereafter, the polysiliconfilm 26 which includes n-type impurities such as phosphorus or arsenicof about 1 ×10¹⁶ to 1×10¹⁸/cm³ or does not include any n-type impurityis formed on the entire surface and etched back, whereby the polysiliconfilm 25 of about 1 nm in thickness is formed as shown in FIG. 14.

91. Then, after forming the polysilicon film 16 on the entire surface tofill up the trench 15 completely, the surface is flattened by CMP in thesame manner as in the first preferred embodiment until reaching the sameheight as the surface of the silicon nitride film 14, and the capacitor22 is formed further thereon.

92. After forming the trench 15, when the polysilicon film 26 is formedbefore forming the n-type polysilicon film 16, a semiconductor, in whichthe polysilicon film 25 is formed on the boundary surface between thestorage node contact 17 and the polysilicon plug 23 as shown in FIG. 15,is obtained.

93. In the manufacturing method of the semiconductor device according tothe second preferred embodiment of the present invention, since thepolysilicon film 25 is formed having a small impurity concentration, ascompared with the storage contact 17 which is formed of polysiliconincluding phosphorus or arsenic of about 1×10²⁰ to 1×10²¹/cm³ as n-typeimpurities, and with the polysilicon plug 23 which includes n-typeimpurities such as phosphorus or arsenic of about 1×10¹⁸ to 1×10²⁰/cm³,resistance of the polysilicon film 25 is increased. As a result, amanufacturing method of the semiconductor device in which the leakagecurrent is restrained from flowing between the storage node 19 and thesource/drain region 6, and the refresh pause time can be prolonged, isachieved.

94. Further, when employing a silicon oxide film which is an insulatingmaterial instead of the polysilicon film 25, the resistance isincreased, and the same advantage of restraining leakage current can beachieved.

95. Further, it is also possible to form a silicon carbide film whichincludes n-type impurities such as nitrogen of about 1×10¹⁸ to1×10²⁰/cm³ in the same manner as in the formation of the polysiliconfilm 25, and when forming such a silicon carbide film, as the energyband gap is increased, it becomes possible to achieve a manufacturingmethod of the semiconductor device in which leakage current can bereduced and a refresh pause time is long.

96. A semiconductor device according to a third preferred embodiment ofthe present invention and a manufacturing method thereof are hereinafterdescribed.

97.FIG. 19 is a sectional view showing the semiconductor deviceaccording to the third preferred embodiment of the present invention.Referring to FIG. 19, reference numeral 28 is a silicon oxide film, andnumeral 29 is a p-type impurity layer. In FIG. 19, like referencenumerals are designated to the same parts as or equivalents in the firstpreferred embodiment.

98. In this semiconductor device, the trench 8 is formed occupying apart of the source/drain regions 5 and 6, and the p-type impurity layer29 including boron, etc. of about 1×10²⁰ to 1×10²¹/cm³ is formed in thep-type semiconductor substrate 1 under the trench 8. The silicon oxidefilm 28 of 1 nm to 10 nm in thickness is formed between the polysiliconplugs 23, 24 and the p-type semiconductor substrate 1, and therefore thep-type semiconductor substrate 1 is not in direct contact with thepolysilicon plugs 23, 24.

99. In the semiconductor device according to the third preferredembodiment of the present invention, a part of the source/drain region 6is replaced with the polysilicon plugs 23, the p-type semiconductorsubstrate 1 is not in direct contact with the polysilicon plugs 23because the silicon oxide film 28 is interposed therebetween, the p-njunction area between the source/drain region 6 and the p-typesemiconductor substrate 1 is reduced thereby reducing a defectivejunction, and leakage current can be restrained, and thus, it becomespossible to achieve a DRAM cell of a long refresh pause time.

100. Further, any pollution on the surface of the source/drain regionsis 6 removed as a result of forming the trench 8, a defective junctionis restrained, and any stress concentrated on the source/drain regionsin the vicinity of ends of the isolating oxide film 2 and on the p-typesemiconductor substrate 1 is reduced, and therefore leakage current canbe reduced and the refresh pause time can be prolonged, eventuallyresulting in an improvement in reliability of the semiconductor device.

101. Further, since the trench 8 is formed also in the part where thesource/drain region 5 is formed in the same manner as the source/drainregion 6, not only is the p-n junction area between the p-typesemiconductor substrate 1 and the source/drain region 5 reduced, therebyreducing a defective junction, but also any pollution on the surface ofthe source/drain regions 5, 6 is removed, and advantages are achievedsuch that a defective junction is restrained, leakage current can bereduced, and drive performance is improved.

102. In a case of placing a greater importance on an improvement ofpunch-through resistance, it is also possible to form the trench 8 onlyon the part of the source/drain region 6 (not illustrated).

103.FIGS. 20, 22 and 23 are sectional views showing sequential steps ofa manufacturing 25 method of the semiconductor device shown in FIG. 19,and FIGS. 21 and 24 are plan views showing a step of the manufacturingmethod of the semiconductor device shown in FIG. 19. Referring to FIGS.20 to 24, reference numeral 30 is a resist, numeral 31 is a siliconoxide film, and broken lines 32 indicate a boundary portion between anactive region and the element isolating oxide film 2.

104. First, after forming the isolating oxide film 2, the gate oxidefilm 3, the gate electrode 4, the source/drain regions 5 and 6, and theside wall 7 on the semiconductor substrate 1, in the same manner as inthe first preferred embodiment, the resist 30 is formed to coat theentire surface, except the surface of the source/drain region 6. FIG. 21is a plan view showing that the mentioned steps have been completed.Then, using the resist 30 and the side wall 7 as masks, an aeolotropicetching is performed, whereby the trench 8 piercing through thesource/drain regions 5 and 6 is formed.

105. Then, as shown in FIG. 22, using the same mask as that for formingthe trench 8, the p-type impurity layer 29 including boron of about1×10²⁰ to 1×10²¹/cm³ is formed on the surface of the p-typesemiconductor substrate 1 where the trench 8 is formed. Although theresist 30 is employed as the mask, it is also preferable to employ asilicon nitride film as the mask.

106. After removing the resist 30, a silicon oxide film 31 is formed bythermal oxidation as shown in FIG. 23.

107. By this oxidation, the surface of the source/drain region 5, thesurface of the source/drain region 6 exposed on the inner wall part ofthe trench 8, and the surface of the p-type semiconductor substrate 1are coated with the silicon oxide film 31. Since the p-type impuritylayer 29 including boron of a high concentration is formed on thesurface of the p-type semiconductor substrate 1 on the bottom surface ofthe trench 8, an accelerated oxidation takes place. Since thesource/drain region 5 is also a high concentration layer of n-typeimpurities, the same accelerated oxidation takes place on the uppersurface thereof. However, by adjusting the concentration of the p-typeimpurity layer 29 and that of the source/drain regions 5 and 6, it ispossible to form the silicon oxide film 31 so that the thickness of thesilicon oxide film 31 formed on the bottom surface of the trench 8 maybe larger than the thickness of the silicon oxide film 31 formed on theupper side of the source/drain region 5.

108. When etching the silicon oxide film 31 entirely, a silicon oxidefilm 31 of 1 nm to 10 nm is formed as shown in FIG. 19.

109. Thereafter, in the same manner as in the second preferredembodiment, the polysilicon plugs 23 and 24 are formed, and the nitrideand oxide films 12 and 13, the silicon nitride film 13, the trench 15,the storage node contact 17, and the capacitor 22 are formed in the samemanner as in the second embodiment.

110. In the manufacturing method of the semiconductor device accordingto the third preferred embodiment of the present invention, since thetrench 8 is formed in a self-aligned manner on a part of thesource/drain region 6, any pollution on the surface of the source/drainregions is removed by simple steps, and an area of the n-p junction isreduced, whereby a defective junction is restrained. In addition, as anystress concentrated on the source/drain region 6 in the vicinity of theend of the isolating oxide film 2 and on the p-type semiconductorsubstrate 1 is reduced, leakage current can be reduced, and the refreshpause time can be prolonged.

111. Further, since the trench 8 and the silicon oxide film 31 areformed also in the part where the source/drain region 5 is formed in thesame manner as the source/drain region 6, not only is the n-p junctionarea between the p-type semiconductor substrate 1 and the source/drainregion 5 reduced, thereby reducing a defective junction, but also anypollution on the surface of the source/drain region 5 is removed, andadvantages are achieved such that a defective junction is restrained,leakage current can be reduced, and drive performance is improved.

112. When forming the mask used at the time of forming the trench 8 soas to expose only the surface of the source/drain region 6 as shown inFIG. 24, the trench 8 is not formed on the source/drain region 5,whereby the punch-through resistance can be improved.

113. A semiconductor device according to a fourth preferred embodimentof the present invention and a manufacturing method thereof arehereinafter described.

114. FIGS. 25 to 28 are sectional views showing the semiconductor deviceaccording to the fourth preferred embodiment of the present invention.Referring to FIGS. 25 to 28, reference numeral 33 is a trench. In FIGS.25 to 28, like reference numerals are designated to the same parts as orequivalents in the foregoing first preferred embodiment.

115. Referring to FIG. 25, in this semiconductor device the trench 33 isformed on a part of the source/drain regions 5 and 6 in such a manner asto be shallower than the n-p junction between the source/drain regions5, 6 and the p-type semiconductor substrate 1.

116. In the semiconductor device shown in FIG. 25 as an exampleaccording to the fourth embodiment of the present invention, as a resultof forming the trench 33, a surface of a part of the source/drainregions 5 and 6 is etched and removed, and not only can a defectivejunction due to pollution around the surface be prevented, but alsostress concentrated on the source/drain region 6 in the vicinity of endsof the isolating oxide film 2 or on the p-type semiconductor substrate 1is reduced, whereby leakage current is reduced.

117. Further, if a fluoride and oxide film is employed as an interlayerinsulating film, for example, and a dielectric constant of this fluorideand oxide film is low as compared with the silicon oxide film, theinterlayer parasitic capacity can be reduced, whereby it is possible toimprove the operating speed of the transistor.

118. It is also preferred that, as shown in FIG. 26, a part 2 a of thesurface of the end of the isolating oxide film 2 is cut to form thepolysilicon plug 23 thereat.

119. In the semiconductor device shown in FIG. 26 as another exampleaccording to the fourth embodiment of the present invention, since thepart 2 a of the end of the isolating oxide film 2 is etched and removed,the area of the polysilicon plug 23 can be larger as compared with thejunction area between the source/drain region 6 and the polysilicon plug23. Accordingly, as the contact resistance becomes small, writeefficiency is improved, and thus it becomes possible to improvereliability in spite of having a fine structure.

120. Furthermore, as a result of removing the part 2 a of the surface ofthe end of the isolating oxide film 2, a junction is formed between thesource/drain region 6 and the semiconductor substrate 1, anddistribution of an impurity concentration varies gently from thesource/drain region 6 to the junction position, which results in a lowelectric field. When the electric field is low, a leakage current due todefects is restrained, and the refresh pause time can be prolonged.

121. This advantage is hereinafter described in detail with reference toa graph of FIG. 29 showing a relation between depth of the semiconductorsubstrate 1 and impurity concentration.

122. The field strength at the n-p junction is decided depending on thejunction concentration and the inclination of the distribution ofimpurity concentration. Generally, when the junction concentration islow, the electric field is low. Further, when the distribution ofimpurity concentration to the junction is gently sloped, the electricfield is low. In a case of the first preferred embodiment, thepolysilicon plug 10 and the semiconductor substrate 1 form the junction.As the distribution of impurity concentration varies sharply from thepolysilicon plug 10 to the junction position, the electric field ishigh. On the other hand, in case of the fourth preferred embodiment, thesource/drain regions 5, 6 and the semiconductor substrate 1 form thejunction. As the distribution of impurity concentration varies gentlyfrom the source/drain regions 5, 6 to the junction position, theelectric field is low. When the electric field is low, any leakagecurrent due to defects is reduced, and the refresh pause time isprolonged, in other words, characteristics of refresh can be improved.

123. Then, as shown in FIG. 27, on the supposition that the length ofthe source/drain region 5 per transistor is “a” and the length of thesource/drain region 6 is “b”, when a≧b an area of the memory cell can bereduced as much as a shortened length of the source/drain region 6.Further, as an area for connecting the polysilicon plug 23 and thesource/drain region 6 becomes smaller, any leakage current due todefects is reduced, and the refresh pause time can be prolonged, andadditionally an advantage is achieved such that as the contact area canbe larger, write efficiency is not lowered. In addition, as thesource/drain region 5 is common for two transistors adjacent to eachother, the length of the source/drain region 5 per transistor is “a”.

124. Further, as shown in FIG. 28, when the surface of the isolatingoxide film 2 is formed higher than the main surface of the p-typesemiconductor substrate 1 and the source/drain regions 5 and 6 areformed very shallow, as it is difficult to make the etching depth in awafer even and shallower than the p-n junction between the source/drainregions 5 and 6 and the p-type semiconductor substrate 1, it is alsopreferred that the trench 33 is formed by cutting only the part 2 a ofthe surface of the end of the isolating oxide film 2.

125. In the semiconductor device shown in FIGS. 27 and 28 as furtherexamples according to the fourth embodiment of the present invention, anarea for connecting the source/drain region 6 and the polysilicon plug23 is reduced, and thereby leakage current can be even furtherrestrained, and the refresh pause time can be prolonged. Further, as thepart 2 a of the surface of the end of the isolating oxide film 2 isremoved, the same advantages as described with reference to FIG. 26 areachieved.

126. FIGS. 30 to 33 are views showing steps of a manufacturing method ofthe semiconductor device according to the fourth embodiment of thepresent invention, and in which FIGS. 30, 31 and 33 are sectional viewsand FIG. 32 is a plan view.

127. First, the manufacturing method of the semiconductor device shownin FIG. 25 is hereinafter described.

128. In the same manner as in the first preferred embodiment, theisolating oxide film 2, the gate oxide film 3, the gate electrode 4, thesource/drain regions 5 and 6, and the side wall 7 are formed on thesemiconductor substrate 1. Then, as shown in FIG. 30, the trench 33which is shallower than the source/drain regions 5 and 6 is formed in aself-aligned manner by a silicon etching material capable of securing alarge selection ratio to the silicon oxide film. Phosphorus ion is theninjected into the entire surface so that the p-n junction between thesource/drain regions 5 and 6 and the p-type semiconductor substrate 1 isdeeper than the bottom surface of the trench 33.

129. Thereafter, in the same manner as in the second preferredembodiment, the polysilicon plugs 23 and 24 are formed, and the nitrideand oxide films 12 and 13, the silicon nitride film 14, the trench 15,the storage node contact 17, and the capacitor 22 are formed in the samemanner as in the second preferred embodiment, and thus the semiconductordevice shown in FIG. 25 is formed.

130. In the semiconductor device shown in FIG. 25 as an exampleaccording to the fourth embodiment of the present invention, since thetrench 33 is formed in a self-aligned manner, a surface of a part of thesource/drain regions 5 and 6 is removed by etching in a simple process,and a defective junction due to pollution around the surface can beprevented. As a result, stress concentrated on the source/drain region 6in the vicinity of the end of the isolating oxide film 2 and on thep-type semiconductor substrate 1 is reduced, whereby it becomes possibleto obtain a semiconductor device in which leakage current is reduced.

131. The manufacturing method of the semiconductor device shown in FIG.26 is now hereinafter described.

132. In the same manner as in the first preferred embodiment, theisolating oxide film 2, the gate oxide film 3, the gate electrode 4, thesource/drain regions 5 and 6, and the side wall 7 are formed. This sidewall 7 is formed of a silicon nitride and oxide film (SiON).

133. As shown in FIG. 31, the isolating oxide film 2 is masked with theresist 30 in such a manner as to coat the surface other than at an end.FIG. 32 is a plan view showing that the mentioned steps have beencompleted. Then, the source/drain regions 5 and 6 and the surface of theisolating oxide film 2 are removed by etching using the side wall 7 andthe resist 30 as masks, whereby the trench 33 which is shallower thanthe source/drain regions 5 and 6 and in which the part 2 a of thesurface of the end of the isolating oxide film 2 is formed as shown inFIG. 26. Thereafter, phosphorus ion is injected into the entire surfaceso that the n-p junction between the source/drain regions 5 and 6 andthe p-type semiconductor substrate 1 is deeper than the bottom surfaceof the trench 33.

134. Since the etching is performed using the side wall 7 and the resist30 formed of the silicon nitride and oxide film (SiON) as the mask, theend of the isolating oxide film 2 of the portion in contact with thesource/drain region 6 is removed in a self-matching manner. As thecontact area of the source/drain region 6 can be secured to be largerand contact resistance becomes small, write efficiency is improved, andthus it becomes possible to achieve a manufacturing method of asemiconductor device in which reliability is improved in spite of havinga fine structure. Further, as the part 2 a of the surface of the end ofthe isolating oxide film 2 is removed, the same advantages as describedwith reference to FIG. 26 are achieved.

135. Then, on the supposition that a length of the source/drain region 5per transistor is “a” and a length of the source/drain region 6 is “b”,when a≦b the semiconductor device shown in FIG. 27 is formed. An area ofthe memory cell can be reduced as much as the shortened length of thesource/drain region 6. Further, as the area for connecting thepolysilicon plug 23 and the source/drain region 6 becomes smaller,leakage current due to defects is reduced, and the refresh pause timecan be prolonged. In addition, as the source/drain region 5 is commonfor two transistors adjacent to each other, the length of thesource/drain region 5 per transistor is “a”.

136. Even when the surface of the isolating oxide film 2 is formedhigher than the principal surface of the p-type semiconductor substrate1 and the source/drain regions 5 and 6 are formed very shallow, afterforming the isolating oxide film 2, the gate oxide film 3, the gateelectrode 4, and the source/drain regions 5 and 6 in the same manner asin the first preferred embodiment, the side wall 7 is formed by etchingback the silicon nitride and oxide film formed on the entire surface.

137. Then, as shown in FIG. 33, a masking is performed with the resist30. The gate electrode 4 formed on the isolating oxide film 2 and theside wall 7 are formed near the center of the isolating oxide film 2with a distance from the boundary between the isolating oxide film 2 andthe active region. Accordingly, when etching in a self-matching mannerby a silicon etching material capable of securing a large selectionratio to the silicon oxide film, only the end of the isolating oxidefilm 2 is removed. In this manner, the trench 33 is formed.

138. Thereafter, in the same manner as in the second preferredembodiment, the polysilicon plugs 23 and 24 are formed, and the nitrideand oxide films 12 and 13, the silicon nitride film 14, the trench 15,the storage node contact 17, and the capacitor 22 are formed in the samemanner as in the second preferred embodiment, and thus the semiconductordevice shown in FIG. 28 is formed.

139. In the semiconductor device shown in FIG. 28 as an exampleaccording to the fourth embodiment of the present invention, since theend of the isolating oxide film 2 is removed even when the surface ofthe isolating oxide film 2 is formed higher than the surface of thep-type semiconductor substrate 1 and the source/drain regions 5 and 6are formed very shallow, a semiconductor device, in which an area forconnecting the source/drain region 6 and the polysilicon plug 23 isreduced, leakage current is restrained, and the refresh pause time isprolonged, can be formed by simple steps. Further, by removing the part2 a of the surface of the end of the isolating oxide film 2, thesource/drain region 6 and the semiconductor substrate 1 form a junction.Accordingly, distribution of the impurity concentration varies gentlyfrom the source/drain regions to the junction position, which results ina low electric field. When the electric field is low, any leakagecurrent due to defects is restrained, and the refresh pause time can beprolonged.

140. Although the bottom surface of the trench 33 formed by cutting theend of the isolating oxide film 2 is coincident to the surface of thesource/drain region 6 in FIG. 33, the same advantages are achieved evenif there is no coincidence between these surfaces.

141. Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

142. Obviously, numerous additional modifications and variations of thepresent invention are possible in light of the above teachings. It istherefore to be understood that within the scope of the appended claims,the present invention may be practiced otherwise than as specificallydescribed herein.

143. The present application is based on Japanese priority document9-326393, the contents of which are incorporated herein by reference.

Claims:
 1. A semiconductor device comprising: a semiconductor substrate;an isolating insulation film formed on an isolated region of a mainsurface of said semiconductor substrate; a pair of source/drain regionsformed in an active region surrounded by the isolated region of the mainsurface of said semiconductor substrate; a trench formed in saidsource/drain regions; a gate electrode formed on a main surface of theactive region of said semiconductor substrate through a gate insulatingfilm; at least one interlayer insulating film formed to coat saidisolating insulation film, said source/drain regions, said trench, andsaid gate electrode; a wiring layer reaching said trench through anopening provided on said at least one interlayer insulating film; and acapacitor connected to one of said pair of source/drain regions throughsaid wiring layer.
 2. A semiconductor device as defined in claim 1 ,wherein said trench is formed deeper into said semiconductor substratethan said source/drain regions, and said wiring layer comprises a firstwiring layer formed by filling up said trench with a material having anenergy band gap larger than silicon, and a second wiring layer connectedto said first wiring layer.
 3. A semiconductor device as defined inclaim 2 , wherein said first wiring layer is composed of siliconcarbide.
 4. A semiconductor device as defined in claim 1 , wherein saidtrench is formed deeper into said semiconductor substrate than saidsource/drain regions, and said semiconductor device further comprises asilicon oxide film formed on a boundary surface between said wiringlayer and said semiconductor substrate.
 5. A semiconductor device asdefined in claim 1 , wherein said trench is formed on a surface of saidsource/drain regions, said one of said pair of source/drain regionsconnected to said capacitor is adjacent to said isolating insulationfilm, and said trench formed on the surface of said source/drain regionsforms a part of a surface of an end of said isolating insulation film.6. A semiconductor device comprising: a semiconductor substrate; anisolating insulation film formed on an isolated region of a main surfaceof said semiconductor substrate; a pair of source/drain regions formedin an active region surrounded by the isolated region of the mainsurface of said semiconductor substrate; a gate electrode formed on amain surface of the active region of said semiconductor substratethrough a gate insulating film; at least one an interlayer insulatingfilm formed to coat said isolating insulation film, said source/drainregions, said trench, and said gate electrode; a wiring layer formed byfilling up a contact hole reaching said source/drain regions through anopening provided on said at least one interlayer insulating film; acapacitor connected to one of said pair of source/drain regions throughsaid wiring layer; and a film restraining a leakage current formed insaid wiring layer apart from said capacitor.
 7. A semiconductor deviceas defined in claim 6 , wherein said wiring layer and said film are bothcomposed of polycrystal silicon, and an impurity concentration of saidfilm is lower than an impurity concentration of said wiring layer.
 8. Asemiconductor device as defined in claim 6 , wherein said film is formedof a silicon oxide film.
 9. A semiconductor device as defined in claim 6, wherein said film is composed of a material having an energy band gaplarger than of said wiring layer.
 10. A semiconductor device as definedin claim 9 , wherein said film is formed of silicon carbide.
 11. Amanufacturing method of a semiconductor device comprising the steps of:forming an isolating insulation film on an isolated region of a mainsurface of a semiconductor substrate; forming a gate electrode on themain surface of said semiconductor substrate through a gate insulatingfilm; forming a pair of source/drain regions in an active regionsurrounded by said isolated region of the main surface of saidsemiconductor substrate; forming a side wall on a side of said gateelectrode; forming a trench by etching said source/drain regions;forming a first wiring layer by filling up said trench with a firstconductive material; forming at least one interlayer insulating film tocoat said isolating insulation film, said source/drain regions, saidtrench, and said gate electrode; forming an opening reaching from asurface of said at least one interlayer insulating film to a surface ofsaid first wiring layer; forming a second wiring layer by filling upsaid opening with a second conductive material; and forming a capacitorconnected to one of said pair of source/drain regions through said firstand second wiring layers.
 12. A manufacturing method of a semiconductordevice as defined in claim 11 , wherein said trench is formed deeperinto said semiconductor substrate than said source/drain regions, andthe first conductive material is composed of silicon carbide.
 13. Amanufacturing method of a semiconductor device as defined in claim 11 ,further comprising the steps of: forming a silicon oxide film by thermaloxidation, after forming said trench deeper into said semiconductorsubstrate than said source/drain regions; and leaving said silicon oxidefilm only on a part of a bottom surface of said trench where saidsemiconductor substrate is exposed, by etching back.
 14. A manufacturingmethod of a semiconductor device as defined in claim 11 , comprising thesteps of: forming a mask coating a surface of said isolating insulationfilm other than at an end of said isolating insulation film; andremoving said one of said pair of source/drain regions to which saidcapacitor is connected and a surface of said isolating insulation filmby etching using the side wall and said mask, and forming a trenchshallower into said semiconductor substrate than said source/drainregion and in which a part of the surface of the end of said isolatinginsulation film is removed.
 15. A manufacturing method of asemiconductor device comprising the steps of: forming an isolatinginsulation film on an isolated region of a main surface of asemiconductor substrate; forming a gate electrode on the main surface ofsaid semiconductor substrate through a gate insulating film; forming apair of source/drain regions in an active region surrounded by saidisolated region of the main surface of said semiconductor substrate;forming a side wall on a side of said gate electrode; forming at leastone interlayer insulating film to coat said isolating insulation film,said source/drain regions, said trench, and said gate electrode; formingan opening for forming a wiring layer connected electrically to one ofsaid pair of source/drain region on said at least one interlayerinsulating film; forming a first wiring layer of said wiring layer byfilling up to about halfway of said opening with a first layer of afirst material; forming a second wiring layer of said wiring layer witha second material placed on the first wiring layer; forming a thirdwiring layer of said wiring layer with a second layer of said firstmaterial placed on the second wiring layer; and forming a capacitorconnected electrically to said wiring layer including said first, secondand third wiring layers.
 16. A manufacturing method of a semiconductordevice as defined in claim 15 , wherein the first and second materialsare both composed of a polycrystal silicon, and the second materialincludes impurities of lower concentration than of the first material.17. A manufacturing method of a semiconductor device as defined in claim15 , wherein said second material is a highly resistant material.
 18. Amanufacturing method of a semiconductor device as defined in claim 15 ,wherein said second material has an energy band gap larger than of saidfirst material.
 19. A manufacturing method of a semiconductor device asdefined in claim 15 , wherein said second material is composed ofsilicon carbide.